WHAT IS THE DIFFERENCE BETWEEN VLSI AND NANO-TECHNOLOGY?
VLSI and nano-technology go almost hand in hand. VLSI stands for Very Large Scale Integration. By integration, I mean getting a large number of complex circuits within a small, defined amount of silicon chip area. The usual method of doing this is as follows.
1. You have a circuit you are ready to put inside a chip and get it fabricated (such circuits are so small and complex that you can't just build them up on a breadboard or fabricate on a PCB).
2. You then look for the various fabrication techniques that are already available. For example, a large number of chips are fabricated using a 180 nm technology. This means the smallest silicon dimension that can be fabricated is of 180 nm. You can't have sizes smaller than this. Various manufacturers (e.g. United Microelectronics-UMC and Taiwan Semiconductor Manufacturing Corp.- TSMC) offer fabrication at various technologies (180 nm/130 nm/90 nm).
3. Once finalized, you convert your working schematic (assuming you've done some rigorous simulations on it) to a mask layout. A layout shows what your chip will look like if you break it open and look inside with a high-powered magnifying glass, so to speak. :P The layout will have components like silicon diffusion area (where the transistor sits), polysilicon layers (to define MOSFET gate terminals), metal layers (for various interconnections across the circuit) etc. The mask layout has to be designed as per the design rules specified by the manufacturer. Rules involve various criteria, usually different line widths and spacings (spacing cannot be below 180 nm in a 180 nm technology for example).
4. You then send the layout to a foundry in either Taiwan or Belgium (that's where most people in IIT Bombay send their layouts) for fabrication.
FOR MORE DETAILS CLICK HERE
VLSI and nano-technology go almost hand in hand. VLSI stands for Very Large Scale Integration. By integration, I mean getting a large number of complex circuits within a small, defined amount of silicon chip area. The usual method of doing this is as follows.
1. You have a circuit you are ready to put inside a chip and get it fabricated (such circuits are so small and complex that you can't just build them up on a breadboard or fabricate on a PCB).
2. You then look for the various fabrication techniques that are already available. For example, a large number of chips are fabricated using a 180 nm technology. This means the smallest silicon dimension that can be fabricated is of 180 nm. You can't have sizes smaller than this. Various manufacturers (e.g. United Microelectronics-UMC and Taiwan Semiconductor Manufacturing Corp.- TSMC) offer fabrication at various technologies (180 nm/130 nm/90 nm).
3. Once finalized, you convert your working schematic (assuming you've done some rigorous simulations on it) to a mask layout. A layout shows what your chip will look like if you break it open and look inside with a high-powered magnifying glass, so to speak. :P The layout will have components like silicon diffusion area (where the transistor sits), polysilicon layers (to define MOSFET gate terminals), metal layers (for various interconnections across the circuit) etc. The mask layout has to be designed as per the design rules specified by the manufacturer. Rules involve various criteria, usually different line widths and spacings (spacing cannot be below 180 nm in a 180 nm technology for example).
4. You then send the layout to a foundry in either Taiwan or Belgium (that's where most people in IIT Bombay send their layouts) for fabrication.
FOR MORE DETAILS CLICK HERE
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