HISTORY OF VERILOG

INTRODUCTION TO VERILOG:

--->verilog standardised as IEEE1364, is a hardware description language and used to model all electronic systems.
--->Verilog is similar like ''C'' LANGUAGE.
--->Verilog simulator was first used beginning in 1985.
--->The implementation was the Verilog simulator sold by Gateway. 
--->The first major extension was Verilog-XL, which added a few features and implemented the infamous "XL algorithm" which was a very efficient method for doing gate-level simulation.
--->Along with other Gateway products, Cadence now became the owner of the Verilog language, and continued to market Verilog as both a language and a simulator.
--->In 1990, Cadence recognized that if Verilog remained a closed language, the pressures of standardization would eventually cause the industry to shift to VHDL.
--->Modelsim (Mentor), a very good mixed language simulator . 
--->The big three simulators (all sign-off quality) are: 
 1) Modelsim [Mentor]
 2) NC-Verilog [Cadence] (derived from Verilog-XL) 
 3) VCS [Synopsys] (derived from Chronologic VCS)
--->After many years, new features have been added to Verilog, and the new version is called Verilog 2001. This version seems to have fixed a lot of problems that Verilog 1995 had. This version is called 1364-2001.
--->Verilog 2005 (IEEE standard 1364-2005) consist of minor connections,spec clarifications and a few language features(such as the uwire keyword).

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