HOW TO GENRATE VCD FILE IN MODELSIM?

GENERATION OF VCDFILE IN MODELSIM:

•  Complete the verilog code.
•  Save and compile the program and simulate the program.
•  Then simulation window will be open,on left hand side corner right click on module go to add    and     select
•   Wave and then select the all  item in region and below on workspace tab. 
•  Go to command window which is in the name Transcript tab.
• There will be an library function (VSIM 6>) type vcd file {module name}v.vcd press enter.
•  Then force the value to the inputs and run, force different inputs and run more than two times. 
•  And again go to command window and type vcd {function of  code} –r/{module name}/* and press enter
• Then break key hit couple of time,vcd file will be generated and close the modelsim tab. 
•   Go and see where your v -file save destination.  

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