TYPES OF MODELING IN VERILOG

Verilog can be designed by following modeling:

--> Switch level modeling

--> Gate level modeling

--> Dataflow modeling

--> Behavioral modeling

--> Structural modeling

INVERTER DESIGN IN VERILOG LANGUAGES 

SWITCH LEVEL MODELING: 

pmos j1(out,in,vdd);
nmos j2(out,in,gnd);

GATE LEVEL MODELING:

not (out,in);

DATAFLOW MODELING:

assign out=~in;


BEHAVIORAL MODELING:

case(in)
1'b0: out=1'b1;
1'b1: out=1'b0;
endcase


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