SKEW:
COUSES OF PROBLEM:
T(skew) >T(clock -q) -T(hold)
T(cycle) =T(d) +T(setup)+T(clock -q)+T(skew)
CLOCK SKEW:
In a synchronous circuit clock skew ( ) is the difference in the arrival time between two sequentially-adjacent registers. Given two sequentially-adjacent registers and with clock arrival times at registerclock pins as and respectively,
- Not all the clock arrives at same time.
- There is an RC-Delay associated with clock wire.
COUSES OF PROBLEM:
- The clock time gets longer.
- The port can get the wrong answer
T(skew) >T(clock -q) -T(hold)
T(cycle) =T(d) +T(setup)+T(clock -q)+T(skew)
CLOCK SKEW:
In a synchronous circuit clock skew ( ) is the difference in the arrival time between two sequentially-adjacent registers. Given two sequentially-adjacent registers and with clock arrival times at registerclock pins as and respectively,
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