SUBTHRESHOLD ADIABATIC LOGIC?

SUBTHRESHOLD ADIABATIC LOGIC: 
Using EKV model , the I–V characteristics of the subthreshold pMOS device can be expressed by

    

  where I0 = 2ηpμpCox(W/L)V 2T . VSG, VSD, and VTH aresource to gate, source to drain, and threshold voltage ofpMOS, respectively. VT = (kT/q) is thermal voltage, ηp issubthreshold slope factor, anD μp is the mobility of pMOSdevice. In subthreshold regime, the threshold voltage (VTH)depends on source to-drain voltage (VSD) through body effect and drain-induced barrier lowering. Considering these effects, threshold voltage can be expressed as follows: 

                        VTH = VTO − γVSB − ηVSD. 

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