DOWN COUNTER WITH T FILPFLOP:
Figure shows a 3-bit counter capable of counting from 0 to 7.he clock inputs of the three flip-flops are connected in cascade. The T input
of each flip-flop is connected to a constant 1, which means that the state of
the flip-flop will be toggled at each active edge (here, it is positive edge)
of its clock. We assume that the purpose of this circuit is to count the number
of pulses that occur on the primary input called Clock.
The modified circuit is shown in
Figure. Here the clock inputs of the second and third flip-flops are driven
by the Q outputs of the preceding stages, rather than by the Q outputs. Figure
4 shows an example timing diagram of such a down-counter.
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