DECODER

DECODER:
--->Decoder is a circuit which is used to convert digital to analog signal
--->It produces single input line and produce multiple output lines.
--->The decoder allows N inputs and generates 2 to the power of N outputs.

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ENCODER

ENCODER:
--->An encoder is a circuit that changes a set of signals into a CODE.
--->It is a multi input combinational logic level circuit that converts the logic level 1 data at its input to an equivalent binary code as output.

--->In the digital domain the easy way of transmission data, it should be encrypted within codes and then transmitted.
--->It is an electronic device used to convert an anlog to digital signal.


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CLOCK DUTY CYCLE?

DUTY CYCLE:

•  Is the percentage of one period in which signal is active.
•  Period: Is the time it takes for a signal to complete one OFF and ON state.
•  If design with 50% of duty cycle which means that:

                                               50%  =ON STATE(Logic 1)
                                               50%  =OFF STATE(Logic 0)

• Duty cycle is depends on period in which it determine the ON-time

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RESIDUE NUMBER SYSTEM

RNS:
--->RNS[Residue Number System]represents a large integer using a set of small integers,so that computation is performed more efficiently.
--->It relies on the Chinese remainder theorem of modular arithmetic.
--->A mathematical idea from (SUN-TSU-SUAN-CHING) in the 4th century AD.
--->A residue number is a set of N integer constants.
--->(m1,m2,m3,.....mn)are refered to as moduli.
--->The residue number system usually uses positional bases that are relatively prime to each other.

--->RNS used in computer applications such as Digital signal processing,fault tolerant application,Cryptography


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CLOCK DESIGN?

DESIGN:

• Pulse mode clocking.
• Edge triggerd clocking.
• Single Phase clocking.
• Two Phase clocking.

Pulse mode clocking:

• Clock is narrow.
• Loop are broken by latch.
• It has  very small clocking overhead.
• It has double sided timing constraints

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CLOCK SKEW?

SKEW:

• Not all the clock arrives at same time.
• There is an RC-Delay associated with clock wire.

COUSES OF PROBLEM:

• The clock time gets longer.
• The port can get the wrong answer

                   T(skew) >T(clock -q) -T(hold)
                    T(cycle) =T(d) +T(setup)+T(clock -q)+T(skew)


CLOCK SKEW:
                             In a synchronous circuit clock skew ( ) is the difference in the arrival time between two sequentially-adjacent registers. Given two sequentially-adjacent registers and with clock arrival times at registerclock pins as and respectively,

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DEMULTIPLEXER

DEMUX:
--->Demultiplexer (or demux) is a device taking a single input signal and selecting one of many data-output-lines, which is connected to the single input. 
--->A multiplexer is often used with a complementary demultiplexer on the receiving end.

--->Increasing the number of signals that get transmitted is even faster.

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CLOCK

CLOCK:

--->The whole reason is why clock is that we want the output to depend on more than just the input,we want it to depends on the previous output too.
--->clock works with Latches or Flipflops to hold state

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HAMMING CODE IN VLSI

HAMMING CODE:
--->In 1954, Richard Hamming invented the (7,4 )code.
--->Hamming code is a set of error-correction codes that can be used to detect and correct bit errors that can occur when computer data is moved or stored.
---> Hamming codes are a class of binary linear codes.
--->Due to the limited redundancy that Hamming codes add to the data, they can only detect and correct errors when the error rate is low.
--->A generalized (7,4)Hamming code is used

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RESISTIVE RANDOM ACCESS MEMORY

RRAM:

--->Resistive random-access memory (RRAM or ReRAM) is a type of non-volatile (NV) random-access (RAM) computer memory that works by changing the resistance across a dielectric solid-state material often referred to as a memristor.
--->Emerging nonvolatile memories (NVMs), such as MRAM, PRAM, and RRAM, have been widely investigated to replace SRAM as the configuration bits in field-programmable gate arrays (FPGAs) for high security and instant power ON.

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SYNCHRONOUS UP COUNTER WITH T FLIPFLOP

SYNCHRONOUS UP COUNTER:

An example of a 4-bit synchronous up-counter is shown in Figure,

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IC FABRICATION POROCESS

IC FABRICATION:

--->There are following types in fabrication.
1)Silicon manifacture
2)􀂄Wafer processing
3)􀂅Lithography
4)􀂅Oxide growth and removal
􀂅5)Diffusion and ion implantation
6)􀂅Annealing
􀂅7)Silicon deposition
􀂅8)Metallization
9)􀂄Testing
10)􀂄Assembly and packaging

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HOW TO DESIGN DOWN COUNTER WITH T FILPFLOP?

 DOWN COUNTER WITH T FILPFLOP:

                      Figure shows a 3-bit counter capable of counting from 0 to 7.he clock inputs of the three flip-flops are connected in cascade. The T input of each flip-flop is connected to a constant 1, which means that the state of the flip-flop will be toggled at each active edge (here, it is positive edge) of its clock. We assume that the purpose of this circuit is to count the number of pulses that occur on the primary input called Clock.

          The modified circuit is shown in Figure. Here the clock inputs of the second and third flip-flops are driven by the Q outputs of the preceding stages, rather than by the Q outputs. Figure 4 shows an example timing diagram of such a down-counter.

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HOW TO DESIGN ASYNCHRONOUS UP COUNTER?

ASYNCHRONOUS COUNTER:

                        Figure shows a 3-bit counter capable of counting from 0 to 7.he clock inputs of the three flip-flops are connected in cascade. The T input of each flip-flop is connected to a constant 1, which means that the state of the flip-flop will be toggled at each active edge (here, it is positive edge) of its clock. We assume that the purpose of this circuit is to count the number of pulses that occur on the primary input called Clock.Thus the clock input of the first flip-flop is connected to the Clock line. The other two flip-flops have their clock inputs driven by the Q output of the preceding flip-flop. Therefore, they toggle their states whenever the preceding flip-flop changes its state from Q=1to Q = 0, which results in a positive edge of the Q signal.

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