What is a "parallel" case statement?

NON-PARALLEL CASE STATEMENT:

Example  shows a casez statement that is not parallel because if the 3-bit irq bus is 3'b011,

3'b101, 3'b110 or 3'b111, more than one case item could potentially match the irq value. This

will simulate like a priority encoder where irq[2] has priority over irq[1], which has priority over

 irq[0]. This example will also infer a priority encoder when synthesized.

module intctl1a (int2, int1, int0, irq);
output int2, int1, int0;
input [2:0] irq;
reg int2, int1, int0;
always @(irq) begin
{int2, int1, int0} = 3'b0;
casez (irq)
3'b1??: int2 = 1'b1;
3'b?1?: int1 = 1'b1;
3'b??1: int0 = 1'b1;
endcase
end
endmodule


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