ADAPTIVE CLOCK GATING:
DCG is difficult to use to reduce power in the SoC
design, which mainly integrates many separated IP cores by bus interconnections.
ACG(Adaptive Clock Gating) analyze the IP model first.
Any IP core (except combinational circuit) can be modeled
as an Finite State Machine (FSM) which includes several states: Idle, Ready,
Run and so on, as shown in the dashed box
When an IP core finishes the work, it enters the idle
state and stay there until it accepts another request from the system bus.
The
clock is disabled automatically not need
the clock. Therefore, ACG disables the IP clock during the output signal is an
active “high“ ; otherwise, the clock is enabled.
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