SUBTHRESHOLD ADIABATIC LOGIC BASED LOGIC GATES:
After verifying the logical functionality, we implemented an SAL-based standard cell library, consisting of common digital gates, such as buffer/inverter, two-input and three-input functions, complex gates, and special gates like half and full adder, which are necessary to implement the 4-bit CLA. The digital gates of the library are developed at transistor level using ramp type supply voltage as discussed in the previous section. Hence, 22-nm technology file is used in our transistor-level designs which guarantee the manufacturability of our designs under all normal conditions with favorable yields.
In Fig, structures of basic logic gates considering SAL are given. These structures resemble either the pull-up or the pulldown network of the static conventional logic. For example, to implement a NAND or a NOR gate, simply the pull-up network can be placed between the supply clock and the output load capacitors, whereas an AND or an OR gate can be implemented using the pull-down network between the supply clock and the output load capacitors. In case of a NAND structure, for every input combination except A = B = 1, the output node voltage will follow the supply clock closely, and we get a triangular output waveform. When A = B = 1 through parallel pMOS transistor, leakage currents will flow as the transistors will behave almost as a constant current source. A very small amount of charge will be stored across the load capacitor, i.e., instead of ground potential, very small voltage will be dropped across the output.
In Fig, structures of basic logic gates considering SAL are given. These structures resemble either the pull-up or the pulldown network of the static conventional logic. For example, to implement a NAND or a NOR gate, simply the pull-up network can be placed between the supply clock and the output load capacitors, whereas an AND or an OR gate can be implemented using the pull-down network between the supply clock and the output load capacitors. In case of a NAND structure, for every input combination except A = B = 1, the output node voltage will follow the supply clock closely, and we get a triangular output waveform. When A = B = 1 through parallel pMOS transistor, leakage currents will flow as the transistors will behave almost as a constant current source. A very small amount of charge will be stored across the load capacitor, i.e., instead of ground potential, very small voltage will be dropped across the output.
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