CLOCK GATING:
Clock gating is a well-known technique to reduce chip dynamic power.
Recent clock gating techniques based on ACG(Adaptive Clock Gating) and instruction level clock gating.
clock gating technique reduces not only switching activity of functional blocks in IDLE state but also dynamic power in running state.
Clock gating is a well-known technique to reduce chip dynamic power.
Recent clock gating techniques based on ACG(Adaptive Clock Gating) and instruction level clock gating.
clock gating technique reduces not only switching activity of functional blocks in IDLE state but also dynamic power in running state.
Clock gating is a
popular technique used in many synchronous circuits for reducing dynamic power
dissipation.
Clock gating saves
power by adding more logic to a circuit to prune the clock tree.
The clock -gating is one of the effective logic
in RTL and architectural power reduction.
By combining(AND gate) the clock with a
gate-control signal, clock gating essentially disables the clock to an IP core
when that IP is not used, avoiding power dissipation due to unnecessary
charging and discharging of the unused circuits.
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