SUBTHRESHOLD ADIABATIC LOGIC FOR ULTRALOW-POWER APPLICATION

SUBTHRESHOLDADIABATIC LOGIC FOR ULTRA LOW-POWER APPLICATION:

In adiabatic logic circuits, ramp type supply voltage is used to slow down the charge transport mechanism.

Hence, the supply clock plays the pivotal role. A ramp type supply voltage φ(t) is considered in Fig., which gradually swings in between logic 0 (Gnd potential) and logic 1 (VDD)in time duration 2T, where f (=1/2T ) is the supply clock’s frequency. The power supply waveform φ(t) can be divided into charging phase, when φ(t) ramps up from 0 to VDD in 0 to T unit time and discharging phase when φ(t) ramps down from VDD to 0 in T to 2T unit time. Considering the charging phase, the voltage at any time instant can be expressed as

                                               

Hence, the behavior of pMOS under high and low VSD will be examined. When we apply logic 1 at the gate of pMOS, VSD becomes high and the drain current can be rewritten as

                       

(1−exp(−VSD/VT )) ∼ 1 when VSD _ VT . Similarly, when we apply logic 0 at the gate of pMOS, very small voltage drops across the transistor. Under this condition, we get

where _V and VOUT are the voltage drops across the resistor and the output node voltage, respectively.

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