HOW TO AVOID NON-"FULL" CASE STATEMENTS?

NON-"FULL" CASE STATEMENTS:

It shows a case statement for a 3-to-1 multiplexer that is not "full" but the case header

includes a "full_case" directive. During Verilog simulation, when binary pattern 2'b11 is driven onto the select lines, the y-output will behave as if it were latched, the same as in Example but the synthesis will treat the y-output as a "don't care" for the same select-line combination, causing a functional mismatch to occur between simulation and synthesis

module mux3b (y, a, b, c, sel);

output y;

input [1:0] sel;

input a, b, c;

reg y;

always @(a or b or c or sel)

case (sel) // synopsys full_case

2'b00: y = a;

2'b01: y = b;

2'b10: y = c;

endcase

endmodule

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