HOW TO AVOID PARALLEL CASE STATEMENT?

PARALLEL CASE STATEMENT:

         Example  is the same as Example 4 except that a Synopsys "parallel_case" directive has been added to the case header. This example will simulate like a priority encoder but will infer nonpriority encoder logic when synthesized.

module intctl1b (int2, int1, int0, irq);

output int2, int1, int0;

input [2:0] irq;

reg int2, int1, int0;

always @(irq) begin

{int2, int1, int0} = 3'b0;

casez (irq) // synopsys parallel_case

3'b1??: int2 = 1'b1;

3'b?1?: int1 = 1'b1;

3'b??1: int0 = 1'b1;

endcase

end

endmodule

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