Friday, 18 December 2015

VERILOG MULTIPLEXER

MULTIPLEXER:

   Module mux2_1(out,control,in1,in2);
   input control,in1,in2;
   output out;
   assign out=control?in1:in2;
   endmodule

--->Conditional expression?true expression:false expression
--->If the control is evaluated it is assigned to 1,then in1 is assigned to out, else in2.

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