NON-"FULL" CASE STATEMENTS

NON-"FULL" CASE STATEMENTS:

It shows a case statement for a 3-to-1 multiplexer that is not "full." The case statement

does not define what happens to the y-output when binary pattern 2'b11 is driven onto the select lines. In this example, the Verilog simulation will hold the last assigned y-output value and synthesis will infer a latch on the y-output as shown in the latch inference

module mux3a (y, a, b, c, sel);

output y;

input [1:0] sel;

input a, b, c;

reg y;

always @(a or b or c or sel)

case (sel)

2'b00: y = a;

2'b01: y = b;

2'b10: y = c;

endcase

endmodule

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