FINAL YEAR VLSI PROJECTS

CLOCK SKEW

CLOCK:
--->The variations in a local clock edge relative to a master clock reference.
--->The difference between arrival times of the clock at different devices is called skew.

FOR MORE REFERENCE CLICK HERE

--->Very Large Scale Integration (VLSI) describes about semiconductor integrated circuits which composed of hundreds of thousands of memory cells logic elements. It is the technique of implementation circuit designing that provides computational speed.

FOR MORE REFRENCE CLICK HERE

CARRY LOOK AHEAD ADDER

CLA:

--->In ripple carry adders, the carry propagation time is the major speed limiting factor.

--->Most other arithmetic operations, e.g. multiplication and division are implemented using several add/subtract steps. Thus, improving the speed of addition will improve the speed of all other arithmetic operations.

--->The addition of two binary numbers in parallel implies that all the bits of augend and addend available for computation at the same time.

--->Pi=Ai^Bi;

--->Gi=Ai&Bi;

--->The output sum and carry can be expressed as

--->Si=Pi^ci;

--->Ci+1=Gi+PiCi;

FOR MORE REFERENCE CLICK HERE

HOW TO AVOID PARALLEL CASE STATEMENT?

PARALLEL CASE STATEMENT:

Example is the same as Example 4 except that a Synopsys "parallel_case" directive has been added to the case header. This example will simulate like a priority encoder but will infer nonpriority encoder logic when synthesized.

module intctl1b (int2, int1, int0, irq);

output int2, int1, int0;

input [2:0] irq;

reg int2, int1, int0;

always @(irq) begin

{int2, int1, int0} = 3'b0;

casez (irq) // synopsys parallel_case

3'b1??: int2 = 1'b1;

3'b?1?: int1 = 1'b1;

3'b??1: int0 = 1'b1;

endcase

end

endmodule

FOR MORE DETAILS CLICK HERE

VEDIC MULTIPLIER

MULTIPLIER:

--->We know general decimal multiplication.

--->We use Binary multiplication.

--->Here i am going to explain Vedic multiplication.

--->Multiplication is one of the main functions in a Digital Signal Processing System. The overall performance of the DSP system depends on the performance of the multiplier.

--->Hence it is very important to develop an efficient and fast design to implement multiplier. Vedic mathematics can be used to transform tedious calculations into simpler and orally manageable operation.

--->Vedic multiplication uses Urdhva Triyambakam multiplication algorithm.

--->The Vedic multiplication algorithm generates partial products in parallel. In this work, we propose using Han-Carlson adder to improve the performance of Vedic multiplier.

FOR MORE REFERENCE CLICK HERE

What is a "parallel" case statement?

NON-PARALLEL CASE STATEMENT:

Example shows a casez statement that is not parallel because if the 3-bit irq bus is 3'b011,

3'b101, 3'b110 or 3'b111, more than one case item could potentially match the irq value. This

will simulate like a priority encoder where irq[2] has priority over irq[1], which has priority over

irq[0]. This example will also infer a priority encoder when synthesized.

module intctl1a (int2, int1, int0, irq);
output int2, int1, int0;
input [2:0] irq;
reg int2, int1, int0;
always @(irq) begin
{int2, int1, int0} = 3'b0;
casez (irq)
3'b1??: int2 = 1'b1;
3'b?1?: int1 = 1'b1;
3'b??1: int0 = 1'b1;
endcase
end
endmodule

FOR MORE DETAILS CLICK HERE

HOW TO AVOID NON-"FULL" CASE STATEMENTS?

NON-"FULL" CASE STATEMENTS:

It shows a case statement for a 3-to-1 multiplexer that is not "full" but the case header

includes a "full_case" directive. During Verilog simulation, when binary pattern 2'b11 is driven onto the select lines, the y-output will behave as if it were latched, the same as in Example but the synthesis will treat the y-output as a "don't care" for the same select-line combination, causing a functional mismatch to occur between simulation and synthesis

module mux3b (y, a, b, c, sel);

output y;

input [1:0] sel;

input a, b, c;

reg y;

always @(a or b or c or sel)

case (sel) // synopsys full_case

2'b00: y = a;

2'b01: y = b;

2'b10: y = c;